With aggressive scaling of complementary metal oxide semiconductor (CMOS) technologies, all-digital phase-locked loops (ADPLLs) have been widely explored due to their features of high re-configurability and on-chip integration of the loop filter. However, the limited frequency resolution of digitally-controlled oscillators (DCOs) becomes a bottleneck in achieving low out-band phase noise of ADPLLs. To achieve frequency resolution in the range of kilohertz (kHz) or even smaller, the minimum switched-capacitor needs to be smaller than atto-Farads (aF). The realization of such capacitors is limited by both lithography and matching. Attempts to scale down the effective capacitance of the switched-capacitor by using capacitive degeneration or transformer coupling are insufficient. Capacitive degeneration would require realizing a small trans-conductance, and transformer coupling would need a small coupling factor to achieve a high scaling factor for scaling down the effective capacitance of the switched-capacitor. Both a small trans-conductance and a small coupling factor are very sensitive to process, supply, and temperate (PVT) variations. Moreover, a high switched-capacitor scaling factor also reduces the fine tuning range of the switched-capacitor, which may cause frequency gaps in the DCO output.
Finally, as compared to radio frequency (RF) DCOs, a smaller tuning capacitor step is required to achieve comparable frequency resolution since mm-Wave DCOs become more sensitive to capacitor variation. As an example, even when using transformer coupling to shrink capacitor tuning step, mm-Wave ADPLLs still need sigma-delta modulators with dithering to further improve frequency resolution, which in turn would require a high clock frequency and large power to suppress out-of-band quantization phase noise.